Which of the following logic families has the maximum noise margin?

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KVS TGT WET (Work Experience Teacher) 23 Dec 2018 Official Paper
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  1. DTL
  2. RTL
  3. ECL
  4. CMOS

Answer (Detailed Solution Below)

Option 4 : CMOS
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Detailed Solution

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NOISE MARGIN:

It represents the amount of noise voltage allowed at the input, which doesn’t affect the standard output.

The noise margin is the amount of noise that could be added to a worst-case output such that the signal can still be interpreted as a valid input.

Noise Immunity:

  • Noise immunity is the amount of noise that can be applied to the input of the gate without causing the gate to change state.
  • There should not be any change in output because of a noise signal. ((b) is correct)

 

F1 S.B Madhu 20.11.19 D 11

  • CMOS has the largest Noise Margin and ECL is having Poor Noise Margin.
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