T Flip Flop MCQ Quiz in తెలుగు - Objective Question with Answer for T Flip Flop - ముఫ్త్ [PDF] డౌన్‌లోడ్ కరెన్

Last updated on Mar 13, 2025

పొందండి T Flip Flop సమాధానాలు మరియు వివరణాత్మక పరిష్కారాలతో బహుళ ఎంపిక ప్రశ్నలు (MCQ క్విజ్). వీటిని ఉచితంగా డౌన్‌లోడ్ చేసుకోండి T Flip Flop MCQ క్విజ్ Pdf మరియు బ్యాంకింగ్, SSC, రైల్వే, UPSC, స్టేట్ PSC వంటి మీ రాబోయే పరీక్షల కోసం సిద్ధం చేయండి.

Latest T Flip Flop MCQ Objective Questions

Top T Flip Flop MCQ Objective Questions

T Flip Flop Question 1:

Which one of the following circuits converts a JK F/F to a T F/F?

  1. F2 Shraddha Neha 12.12.2020 D3
  2. F2 Shraddha Neha 12.12.2020 D4
  3. F2 Shraddha Neha 12.12.2020 D5
  4. F2 Shraddha Neha 12.12.2020 D6

Answer (Detailed Solution Below)

Option 1 : F2 Shraddha Neha 12.12.2020 D3

T Flip Flop Question 1 Detailed Solution

Concept:

T FF truth table

T

Qn

Qn+1

0

0

0

0

1

1

1

0

1

1

1

0

 

JK FF excitation table.

Qn

Qn+1

J

K

0

0

0

X

0

1

1

X

1

0

X

1

1

1

X

0

 

Analysis:

In this question, we want to convert the JK flip-flop into T FF.

Conversion of FF is a 3 step process which is given below.

Step 1:

Construct the characteristic table of TFF (which we want to make) and excitation table of JK FF (which is given)

T

Qn

Qn+1

J

K

0

0

0

0

X

0

1

1

X

0

1

0

1

1

X

1

1

0

X

1

 

Step 2:

Using the K-map find the Boolean expression for J and K in terms of T

F1 Shraddha Neha 22.01.2021 D 1

 

F1 Shraddha Neha 22.01.2021 D 2

\(\left. {\begin{array}{*{20}{c}} {J = T}\\ {K = T} \end{array}} \right\}\)

Step 3:

Construct the circuit diagram

F1 Shraddha Neha 22.01.2021 D 3

T Flip Flop Question 2:

If the Duty Cycle of Clock applied is 50%  then what is the Duty Cycle of the Signal Generated at Output

EC Digital Electronics Chapter test 3 final Images-Q20

  1. 50%

  2. 75%

  3. 25%

  4. 100%

Answer (Detailed Solution Below)

Option 3 :

25%

T Flip Flop Question 2 Detailed Solution

The Duty cycle of clock = 50%,

 Hence Wave Form of Clock is as follows and T – F/F divides frequency by 2

EC Digital Electronics Chapter test 3 final Images-Q20.1

∴ Duty Cycle Of Output Waveform \(= \frac{{{T_{ON}}}}{{{T_{ON}} + {T_{OFF}}}} \times 100\)

\(= \frac{{\frac{1}{4}}}{{\frac{1}{4} + \frac{3}{4}}} \times 100 = 25\%\)

Important: The Toggle flip-flops acts like a mod – 2 (or) Divided by 2 Counter.

T Flip Flop Question 3:

GATE EE  Digital Electronic  Chapter 3 Q12

What is represented by the digital circuit given above:

  1. An SR flip – flop with A = S and B = R

  2. An JK flip – flop with A = K and B = J

  3. An JK flip – flop with A = J and B = K

  4. An SR flip – flop with A = R and B = S

Answer (Detailed Solution Below)

Option 3 :

An JK flip – flop with A = J and B = K

T Flip Flop Question 3 Detailed Solution

For T. FF ⇒ Q(t+1) = T ⊕ Q

But \(T\; = \;A\;\bar Q + BQ\)

\(\Rightarrow Q\left( {t + 1} \right) = \left( {A\bar Q + BQ} \right) \oplus Q\)

\(\Rightarrow Q\left( {t + 1} \right) = A\bar Q + \bar BQ\)

\(Q\left( {t + 1} \right) = J\bar Q + \bar KQ\)

\(\Rightarrow J = A,\;K = B\)

T Flip Flop Question 4:

A 100 kHz square waveform is applied to the clock input of the flip-flop shown below. The frequency of Q output will be -

qImage672a59c975ed3edab9cc8eba

  1. 100 kHz
  2. 200 kHz
  3. 50 kHz
  4. Zero

Answer (Detailed Solution Below)

Option 1 : 100 kHz

T Flip Flop Question 4 Detailed Solution

Calculation:

We are given that a 100 kHz square waveform is applied to the clock input of the flip-flop.

For a flip-flop, the output frequency is typically half of the input clock frequency, because a flip-flop toggles its state on each clock pulse. This means that for every two input pulses, the output changes state once.

Therefore, if the input frequency is 100 kHz, the output frequency will be:

Output frequency = Input frequency / 2

Substituting the given input frequency:

Output frequency = 100 kHz / 2 = 50 kHz

Hence, the frequency of Q output will be 50 kHz.

Final Answer: The correct answer is option 3: 50 kHz.

T Flip Flop Question 5:

Which one of the following circuits converts a JK F/F to a T F/F?

  1. F2 Shraddha Neha 12.12.2020 D3
  2. F2 Shraddha Neha 12.12.2020 D4
  3. F2 Shraddha Neha 12.12.2020 D5
  4. F2 Shraddha Neha 12.12.2020 D6
  5. None of these

Answer (Detailed Solution Below)

Option 1 : F2 Shraddha Neha 12.12.2020 D3

T Flip Flop Question 5 Detailed Solution

Concept:

T FF truth table

T

Qn

Qn+1

0

0

0

0

1

1

1

0

1

1

1

0

 

JK FF excitation table.

Qn

Qn+1

J

K

0

0

0

X

0

1

1

X

1

0

X

1

1

1

X

0

 

Analysis:

In this question, we want to convert the JK flip-flop into T FF.

Conversion of FF is a 3 step process which is given below.

Step 1:

Construct the characteristic table of TFF (which we want to make) and excitation table of JK FF (which is given)

T

Qn

Qn+1

J

K

0

0

0

0

X

0

1

1

X

0

1

0

1

1

X

1

1

0

X

1

 

Step 2:

Using the K-map find the Boolean expression for J and K in terms of T

F1 Shraddha Neha 22.01.2021 D 1

 

F1 Shraddha Neha 22.01.2021 D 2

\(\left. {\begin{array}{*{20}{c}} {J = T}\\ {K = T} \end{array}} \right\}\)

Step 3:

Construct the circuit diagram

F1 Shraddha Neha 22.01.2021 D 3

T Flip Flop Question 6:

If the input to T flip flop is 100 Hz signal, the final output of the three T flip flops in cascade is__ (in Hz)

Answer (Detailed Solution Below) 12 - 13

T Flip Flop Question 6 Detailed Solution

In T flip flop the output frequency will become half of the input frequency. Here three T flip flops connected in cascade mode.

The output frequency, \({f_o} = \frac{1}{8} \times 100 = 12.5\;Hz\)

T Flip Flop Question 7:

A counter made of T flip-flop counts digits according to 2421 (\({{\rm{Q}}_{\rm{A}}}{{\rm{Q}}_{\rm{B}}}{{\rm{Q}}_{\rm{C}}}{{\rm{Q}}_{\rm{D}}}\)) code.  

The input \({{\rm{T}}_{\rm{B}}}\) is 

  1. \({{\rm{\bar Q}}_{\rm{A}}}{{\rm{Q}}_{\rm{B}}} + {{\rm{Q}}_{\rm{C}}}{{\rm{Q}}_{\rm{D}}}\)
  2. \({{\rm{Q}}_{\rm{A}}}{{\rm{\bar Q}}_{\rm{B}}} + {{\rm{Q}}_{\rm{C}}}{{\rm{Q}}_{\rm{D}}}\)
  3. \({{\rm{Q}}_{\rm{A}}}{{\rm{Q}}_{\rm{B}}} + {{\rm{\bar Q}}_{\rm{C}}}{{\rm{Q}}_{\rm{D}}}\)
  4. \({{\rm{Q}}_{\rm{A}}}{{\rm{Q}}_{\rm{B}}} + {{\rm{Q}}_{\rm{C}}}{{\rm{\bar Q}}_{\rm{D}}}\)

Answer (Detailed Solution Below)

Option 1 : \({{\rm{\bar Q}}_{\rm{A}}}{{\rm{Q}}_{\rm{B}}} + {{\rm{Q}}_{\rm{C}}}{{\rm{Q}}_{\rm{D}}}\)

T Flip Flop Question 7 Detailed Solution

The present state next state and excitation table of the counter is

Untitled123121

Live test 3 Images Q13a

Live test 3 Images Q13b

T Flip Flop Question 8:

live 1 digitL 3

The above circuit can be used as clock generator if 

  1. \(\rm X=0\)
  2. \(\rm X=1\)
  3. \(\rm X=0 \ or \ 1 \)
  4. \(\rm {X=Y}\)

Answer (Detailed Solution Below)

Option 2 : \(\rm X=1\)

T Flip Flop Question 8 Detailed Solution

XOR gate with one input terminal HIGH acts as an inverter. Thus if \(\rm X=1\) the circuit will acts as a ring oscillator with 3 inverting stages

T Flip Flop Question 9:

The output frequency of a frequency divider circuit that contains 12 flip – flops with an input clock frequency of 20.48 MHz is ______ (in kHz)

Answer (Detailed Solution Below) 5

T Flip Flop Question 9 Detailed Solution

Each flip – flop divides the input frequency by 2. Thus after 12th flip – flop the frequency will be

\(\begin{array}{l} = 20.48/{2^{12}}\\ = \frac{{20.48}}{{4096}}\ MHz\\ = 0.005\ MHz\\ = 5\ kHz \end{array}\)

T Flip Flop Question 10:

The logic circuit shown below. Find the  frequency of output in GHz assume propagation delay of

X–NOR gate is zero. The wave form of input A and clk is given below.

GATE EC PART TEST 2 Images-Q.12

GATE EC PART TEST 2 Images-Q.12.1

Answer (Detailed Solution Below) 0

T Flip Flop Question 10 Detailed Solution

The output of X-NOR gate \(= AB + \bar A\bar B = \bar A\)

and here T – Flip flop is negative triggered ,So the wave forms of output is as follows

GATE EC PART TEST 2 Images-Q.12.2

Time period of output = ∞

Frequency of output = 0 GHz

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