Logic Gates MCQ Quiz - Objective Question with Answer for Logic Gates - Download Free PDF

The correct option is 4

Concept:

From the truth table, it is clear that the output of an EX-OR gate is '0' when both inputs are '1'. This is because the EX-OR gate outputs '1' only when the inputs are different. When both inputs are the same (either both 0 or both 1), the output is '0'. Therefore, the correct answer is option 4.

The primary goal of simplifying a Boolean expression before implementing it with gates is: 3) To reduce the number of gates and interconnections

Explanation:

• Minimizing gates reduces the circuit's cost, complexity, and physical space required.
• Fewer interconnections improve reliability (less chance of wiring errors or signal interference).
• Optimized circuits consume less power and operate faster (fewer propagation delays).

Concept:

The given Boolean function is \( F(A, B, C) = AB' + BC + AC \).

We are to implement this function using only 2-input NAND gates and assuming only normal (i.e., uncomplemented) inputs are available.

Step-by-step NAND Implementation:

1. Generate B’:
Using NAND gate: \( B' = B \text{ NAND } B \) → 1 gate

2. Generate AB’:
Use NAND to AND: \( A \cdot B' = (A \text{ NAND } B') \text{ NAND } (A \text{ NAND } B') \) → 2 gates

3. Generate BC:
\( BC = (B \text{ NAND } C) \text{ NAND } (B \text{ NAND } C) \) → 2 gates

4. Generate AC:
\( AC = (A \text{ NAND } C) \text{ NAND } (A \text{ NAND } C) \) → 2 gates

5. ORing all three terms:
To implement \( AB' + BC + AC \), we use NAND-based OR with DeMorgan’s law:
\( A + B = (A' \cdot B')' \) → Requires 2 NANDs for each OR combination.
Three terms OR can be done in 3 NAND gates optimally.

Total NAND Gates Required:

• 1 (B’)
• 2 (AB’)
• 2 (BC)
• 2 (AC)
• 3 (Final OR)

Total = 1 + 2 + 2 + 2 + 3 = 10 gates

Optimization:

With gate sharing and smart logic restructuring, it is possible to reduce the count. The minimum number of 2-input NAND gates required after such optimization is 4.

Concept:

Logic Gate Analysis: The given logic circuit consists of a combination of **NOR, NAND, and OR gates**.

• Step 1: NOR Gate Output
  • The NOR gate receives inputs A and B.
  • The output of the NOR gate is:
  • Q = A + B
• Step 2: NAND Gate Output
  • The NAND gate receives inputs A and B.
  • The output of the NAND gate is:
  • P = A ⋅ B
• Step 3: OR Gate Output
  • The OR gate receives the outputs of the NOR and NAND gates.
  • Final output Y is:
  • Y = Q + P
  • Y = A + B + A ⋅ B

Calculation:

Expanding the expression:

⇒ Y = A + B + A ⋅ B

⇒ Using De Morgan’s Theorem:

⇒ A + B = A ⋅ B

⇒ A ⋅ B = A + B

⇒ Y = (A ⋅ B) + (A + B)

⇒ Using Distribution: Y = A + B

⇒ Y = A ⋅ B

∴ The circuit behaves as a NAND gate.

Explanation:

(A) The output of an EX-OR gate is a logic '1' when the inputs are unlike and a logic '0' when the inputs are like.

Correct. An Exclusive OR (EX-OR) gate outputs '1' when the inputs are different (unlike), and '0' when the inputs are the same (like).

(B) The output of a NAND gate is a logic '1' when all its inputs are a logic '1'.

Incorrect. A NAND gate gives a logic '1' when not all inputs are '1'. If all inputs are '1', the output is '0'. Therefore, this statement is wrong.

(C) The output of a two-input EX-NOR gate is a logic '1' when the inputs are like and a logic '0' when they are unlike.

Correct. An Exclusive NOR (EX-NOR) gate outputs '1' when the inputs are the same (like) and '0' when they are different (unlike).

(D) Shorting the inputs of a NOR gate gives a NOT circuit.

Correct. When you connect both inputs of a NOR gate together, it behaves as a NOT gate. The output is '1' when the input is '0' and '0' when the input is '1'.

The correct statements are (A), (C), and (D).

Thus, option '1' is correct.

Concept:

XNOR Gate:

Symbol:

Truth Table:

Output Equation: \(Y={\overline{A\oplus B}}\)

1) If B is always Low, the output is the inverted value of the other input A, i.e. A̅.

2) The output is low when both the inputs are different.

3) The output is high when both the inputs are the same.

4) XNOR gate produces an output only when the two inputs are same.

Analysis:

\(F = \overline{A+0}=\bar A\)

The number of 2-input NAND gates required to implement a 2-input XOR gate is 4.

Similarly, the number of 2-input NOR gates required to implement a 2-input XNOR gate is 4.

XOR GATE

Symbol:

Truth Table:

Output Equation: \(Y = {\bf{A}} \oplus {\bf{B}} = \bar AB + A \bar B\)

Key Points: 

1) If B is always High, the output is the inverted value of the other input A, i.e. A̅.

1) The output is low when both the inputs are the same. 

2) The output is high when both the inputs are different.

Explanation:

\(Y = {\bf{\bar X}} \oplus {\bf{X}} = \bar{\bar X} X+\bar X \bar X\)

\(Y = XX+\bar X \bar X\)

\(Y = X+\bar X \)

Y = 1

\(Q = \overline {AB} \)

Output expression Q is equivalent to NAND gate.

Important Points

NAND GATE

Symbol:

Truth Table:

Output Equation: \(Y = \overline {A.B} = \overline A + \overline B\)

Key Points:

1) If A is always High, the output is the inverted value of the other input B, i.e. B̅

2) The output is low only when both the inputs are high

3) It is a universal gate

Concept:

Propagation Delay:

The propagation delay, or gate delay, is the length of time that starts when the input to a logic gate becomes stable and valid to change, to the time that the output of that logic gate is stable and valid to change.

T = 2n Tpd

Here 2 is multiplied with the propagation delay when logic gates are connected in feedback.

T is the time period of the output

n is the number of logic gates

Tpd is the propagation delay of one gate

Calculation:

Given, 

n = 3 as there are three gates with feedback

Tpd = 100 nsec

T = 2 × 3 × 10^-7

T= 6 × 10-7

Fundamental Frequency is given by f

\(f=\frac{1}{T}\)

\(f=\frac{1}{6 \ × \ 10^{-7}}\)

f = 1.67 × 10⁶

f = 1.67 MHz

Concept:

In Digital Electronics, Logic 1 means High and Logic 0 means low.

Whenever in diode, if 1 is applied to anode and 0 to cathode then Diode acts as a short circuit i.e. ON.

And if 0 is applied to anode and 1 to cathode Diode acts as open circuit i.e. OFF.

Explanation:

The given logic circuit is

For different logic of A and B,4 cases are there and according to that logic of C will vary.

Case 1

When A is logic 0 and B is logic 0

Then the logic of C will be 0.

Case 2

When A is logic 0 and B is logic 1

Then the logic of C will be 1.

Case 3

When A is logic 1 and B is logic 0

Then the logic of C will be 1.

Case 4

When A is logic 1 and B is logic 1

Then the logic of C will be 1.

According to Result, we make a table

This Table is of Logic OR gate.

∴ C = A + B

Important Points

Logic Circuit for AND gate is C = AB

The given gate is an XNOR gate. NOR gate is an OR gate followed by a NOT gate.

Symbol:

Truth Table:

Output Equation: \(Y={\overline{A\oplus B}}\)

Key Points: 

1) If B is always Low, the output is the inverted value of the other input A, i.e. A̅.

1) The output is low when both the inputs are different.

2) The output is high when both the inputs are the same.

The figure below shows the IEEE/ANSI symbols alongside the traditional symbols for the basic gates:

Concept:

3 variable K-maps:

• For a 3-variable Boolean function, there is a possibility of 8 output minterms.
• The general representation of all the minterms using 3-variables is shown below.

Calculation:

Given Boolean expression is,

F = AB + AC̅ + BC

= A B C̅ + A B C + A B̅ C̅ + A B C̅ + A B C + A̅ B C

\(= \sum \left( {{m_6},\;{m_7},\;{m_4},\;{m_6},\;{m_7},\;{m_3}} \right)\)

\(= \sum \left( {{m_3},\;{m_4},\;{m_6},\;{m_7}} \right)\)

F = BC + AC̅

NOR gate:

• It is a digital circuit having two or more inputs but only one output.
• It gives a high output if either input A or B or both are low (0) otherwise it gives a high output (1).
• It is described by the Boolean expression: \(\overline {A + B} = Q\)
• The above logic gate is the NOR gate.

The truth table for NOR gate:

Logic gates:

• A logic gate is an idealized or physical electronic device implementing a Boolean function.

• A logical operation performed on one or more binary inputs that produce a single binary output.

If A and B are given as input then:

LOGIC GATE	OUTPUT	Diagram
OR	A + B
AND	A.B
NAND	\(\overline {A.B} \)
NOR	\(\overline {A+B} \)
XOR	\(A\bar B + \bar AB\)
XNOR	A.B + \(\overline {A.B} \)